Integrated circuits (ICs), especially analog or linear circuits such as phase lock loop circuits or voltage controlled oscillators, as well as radio frequency (RF) circuits often include an inductor. Such circuits are often combined with other circuits such as microprocessors to form an integrated circuit system. The various circuits may each be realized as a separate semiconductor chip or die, and as such may be combined on a circuit board, in either a planar or stacked array, to form the integrated circuit system.
Inductors having a high quality factor (“Q”) have been difficult to achieve in an integrated form on an IC, especially in view of the trend toward including more and more complexity on the IC. The quality factor of an inductor is the ratio of its inductive reactance to its resistance at a given frequency and is a measure of the efficiency of the inductor. The higher the Q factor, the closer the inductor approaches the behavior of an ideal, lossless inductor. Inductance of an inductor is proportional to loop area (the area circumscribed by the inductor) times the number of turns (the number of times the inductor circumscribes that area). Integrated inductors having a high inductance generally require a large surface area (i.e., a large loop area) on a semiconductor chip, and the need for a large surface area runs counter to the trend toward more complexity with more devices on a chip. If the inductor is fabricated as a multi-level loop to save surface area, the Q of the inductor suffers because of the high resistance of vias between metal levels combined with an increase in parasitic capacitance.
Accordingly, it is desirable to provide integrated circuit systems having high inductance, high Q inductors. In addition, it is desirable to provide integrated circuit systems that include vertical inductors realized through the use of through substrate vias (TSVs). Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.